In reply to chr_sue:
In reply to yasaswi93:
Thanks for sharing your code. Unfortunately the interesting piece of code was missing. item_t.
Please provide it.
It is this:
class item extends uvm_sequence_item;
rand trans_type_e m_trans_type;
rand hdr_t m_hdr;
rand logic [127:0] m_data;
`uvm_object_utils(item)
extern function new(string name="item");
endclass : item
Another remarks:
(1) Using the process variables is not relevant in the UVM. You can remove it. This makes your code more easy.
-Sure.
(2) Do you have low-active reset. The namimg looks like this. In the code your reset is considered as high active.
-It’s active low and there is no issue in the reset logic I think.
(3) You could randomize the delay _cycles outside of the driver, by putting it to the seq_item item_t.
-But these delay parameters are from cfg class. So having cfg handle in every transaction didn’t seem to be good idea to me.