Suggestions for basic SystemVerilog/UVM projects for freshers

UVM
1

Hi all,

I’m looking for suggestions on basic SystemVerilog and UVM projects that freshers can work on to build hands-on verification experience.

A few ideas I have in mind so far:

  • Synchronous/asynchronous FIFO or simple memory with a class-based SV testbench
  • ALU or counter with constrained-random stimulus and functional coverage
  • UART, SPI or I2C controller with a complete UVM environment (agent, sequencer, driver, monitor, scoreboard)
  • APB or AHB-Lite slave with a UVM register model (RAL)

Questions:

  1. What other designs would you recommend for someone just starting out?
  2. Are there any open-source DUTs or reference testbenches (GitHub, EDA Playground, etc.) that are good starting points?
  3. Which concepts (assertions, coverage, RAL, virtual sequences, etc.) should a beginner project aim to cover?

Any pointers or resources would be really appreciated. Thanks!