In reply to chr_sue:
Sorry in case code snippet mislead to wrong interpretation of code. Apologies for the same. Indeed I do have data processing which is performed at various times when monitor sends data at different time. Here idea is that post processing, some new information is generated which is contained inside scoreboard, I am looking to provide this information to other verification component in testbench environment.
`uvm_analysis_imp_decl(_inp_1)
`uvm_analysis_imp_decl(_inp_2)
class my_scb extends uvm_component;
`uvm_component_utils(my_scb);
uvm_analysis_imp_inp_1 #(inp_1_tr, my_scb) inp_1_exp;
uvm_analysis_imp_inp_2 #(inp_1_tr, my_scb) inp_2_exp;
function void write_inp_1(inp_1_tr tr);
// process data and push in inp_q_1
endfunction
function void write_inp_2(inp_2_tr tr);
// process data and push in inp_q_2
endfunction
task run_phase();
// wait for some particular data in inp_q_1
// find some information from inp_q_2
// generate useful info say info_tr
// info_tr - this information is needed by other verif component
// is it okay to sent via analysis port like usually monitor do?
endtask
uvm_analysis_port #(info_tr) scb_ap; // is this okay
endclass
class other_comp extends uvm_component;
// this guy needs info_tr
endclass