Structure and union

SystemVerilog
,
4

In reply to dave_59:

Does SV support these constructs?
union packed {
rand bit [7:0] B[4];
rand bit [15:0] C[2];
} ABC_u;

class packed {
rand bit [7:0] B[4];
rand bit [15:0] C[2];
} ABC_c;

Thanks.