Streaming operator

SystemVerilog
3

In reply to dave_59:

In reply to verif_learner:
If you want to know, read section 11.4.14 Streaming operators (pack/unpack) of the 1800-2017 LRM and then ask a more specific question that you need help with.

Thanks. I have started going through LRM. I am not done yet with the section fully but I do have two questions.

I assume that streaming operator can also be used to convert array of one dimension to another array of a different dimension. In this context, I have a question whether to use the steaming operator on the RHS or on the LHS. A simple example does now show any difference though. I am probably missing some basic concept of streaming operator and hence this question.

The example is shown below:

module x;
  bit [1:0] arr_1[0:1] = {2'b01, 2'b01};
  bit [3:0] arr_2;
  bit [3:0] arr_3;
  bit arr_4[0:3];
  bit arr_5[0:3];
  
  initial begin
    {>>{arr_2}} = arr_1;
    {<<{arr_3}} = arr_1;
    {>>{arr_4}} = arr_1;
    arr_5 = {<<{arr_1}};
    
    $display ("%p ", arr_2);
    $display ("%p ", arr_3);
    $display ("%p ", arr_4);
    $display ("%p ", arr_5);
  end
endmodule

Output:

5
10
'{'h0, 'h1, 'h0, 'h1}
'{'h1, 'h0, 'h1, 'h0}

Please see the display for arr_4 and arr_5.

Question 2:
Are streaming operators fundamentally related to packed or unpacked arrays.
The literature seem to use these two together while describing.
I am not sure if the document mean, unpacking/packing an array or packed/unpacked array.
This is a bit confusing.