Std::randomize question

SystemVerilog
6

Thanks ABD :) I slightly modified it. but mostly your code fits my need.



// Code your testbench here
// or browse Examples
class test;
 
 // int prev_a ;
 
  task hello(  );
    int a,prev_a;    // automatic variable , will  exist  per call .
 
    if( std::randomize(a) with {a inside {0,4'b1111}; if (a==4'b1111)a != prev_a ; } ) 
     begin
      prev_a = a ; 
      $display ("a value is %d",a);
    end  
  else
      $display (" Randomization Failed ");
 
  endtask
 
endclass
 
module tb;
  test t1;
 
  initial begin
  
 
    t1 = new();
    repeat (10) begin
 
    //if (!t1.randomize()) $display ("Error");
      t1.hello(  ); 
 
  end
  end
 
endmodule