Std::randomize question

SystemVerilog
2

In reply to rag123:

One possible solution ::


class test;
  
  int prev_a ;
  
  task hello( inout int prev_a );
    int a;    // automatic variable , will  exist  per call .

   if( std::randomize(a) with {a inside {0,4'b1111}; a != prev_a ; } ) 
     begin
      prev_a = a ; 
      $display ("a value is %d",a);
    end  
  else
      $display (" Randomization Failed ");

  endtask
 
endclass
 
module tb;
  test t1;
  
  initial begin
   int previous_a ;
  
    t1 = new();
    repeat (10) begin
      
    //if (!t1.randomize()) $display ("Error");
      t1.hello( previous_a ); 
      
  end
  end
 
endmodule