Static vs Automatic

SystemVerilog
,
4

In reply to mukul1996:

You are correct, in that the last update which got executed will be the final value.

However, when you call update, you also immediately call $display, so the value is updated with the argument that is passed in and then displayed. There is nothing blocking between the assignment and $display to allow any task switching.

A better example would decouple the update and display:


class a;
  static int b;
  
  static function void print();
    $display("At time %0d The value of b is = %0d", $time, b);
  endfunction
  
  static function void update(int c = 0);
    b = c;
    print();
  endfunction
endclass
 
module check();
  a a1;
 
  initial begin
    a1 = new();
    fork
      begin
        #3 a1.update(4); // Update @time 3
        #1 a1.print();   // Display @time 4
        #3 a1.print();   // Display @time 7
      end
      begin
        #5 a1.update(5); // Update @time 5
        #1 a1.print();   // Display @time 6
      end
    join
  end
endmodule