Static variable in parametric class

SystemVerilog
,
2 
class A #(int a = 10);
static int b = a;
static int c ;
endclass
module main;
A #(30) a1;
A #(50) a2;
initial begin
a1 = new();
a2 = new();
if(!$cast(a1,a2))
  $display("Error");
$display ("a1.b =%0d,\t a2.b=%0d,\t a1.c= %0d,\t a2.c = %0d",a1.b,a2.b,a1.c,a2.c);
a1.b = 111;
a1.c = 121;
$display ("a1.b =%0d,\t a2.b=%0d,\t a1.c= %0d,\t a2.c = %0d",a1.b,a2.b,a1.c,a2.c);
end
endmodule

Output:

Error

a1.b =30, a2.b=50, a1.c= 0, a2.c = 0

a1.b =111, a2.b=50, a1.c= 121, a2.c = 0

It means assignment to object of class A #( 30) from object of class A #( 50) is illegal which says both are different classes. And Static works for objects of single(same) class.

Thanks,
Rajashekhar.