Stability signal when another signals is asserted

UVM
,
13

In reply to kevinvig:

I don’t know why my simulator doesn’t recognize the “until” keyword

Seems like a tool limitation . 3 out of the 4 tools on edaplayground support ’ until ’ operator .

Is there another alternative to write this in a clear way?


property dout_stable_property;
    @(posedge clk) $rose( cs ) |=> ( $stable( dout ) throughout ( $fell( cs ) ) [->1] );
 endproperty

This is supported on all 4 tools available on edaplayground .