Solve-Before Constraints

SystemVerilog
2

In reply to Husni Mahdi:

A few things to note about your constraints :

  1. Randomization generates 2-state values only . This means although load is 4-state type , it would only have 2-state values 0 / 1 .
load dist {0:=1, 1:=1};

Hence this would be redundant as load would have these 2 values with equal probability even without the constraint .
2.

data inside {[0:8'hff]};

data is 8-bit variable which means the solution space varies from 0 to 8’hFF without the constraint as well .
Hence this constraint is redundant as well .
3. If load != 1 , data is unconstrained . This means data can take any value from it’s solution space.
Hence your observation :

But data is generated regardless of load.

solve load before data;

Even without this constraint the probability remains the same . Hence this would be redundant as well .

I believe your requirement is :


constraint DATA_GEN { if(load == 0 ) data == const'( data ) ; }