Soft constraints vs Hard constraints

SystemVerilog
,
5

In reply to Sharandiva:

Just to add, nothing in your second example can result in ignoring the soft constraints. Since test_config.var1 and test_config.var2 depend on cfg[0/1].var1 and cfg[0/1].var2, if you have additional constraints on test_config.var1/var2 that would contradict with the soft constraints, this could result in the behavior you are seeing. For example:


if ( cfg[0].enable)
      var1 == cfg[0].var1;
      var1 != cfg[1].var1; //contradicts soft constraints
    else {
      var1 == cfg[1].var1;
      var1 != cfg[0].var1; //contradicts soft constraints
    }

So a full example will clear any remaining confusion.