Soft constraints vs Hard constraints

SystemVerilog
,
3

In reply to dave_59:

Here is the complete code:
There are 2 levels of hierarchy.

class config_object;
  rand int unsigned var1, var2;
  rand enable;
  constraint c_default {
    soft var1 == 10;
    soft var2 == 15;  
  }
  constraint c_var1 {
    var1 inside {9,10,11,12};
  }
  constraint c_var2 {
    var2 inside {14,15,16,17}; 
  }
endclass

class test_config;
  rand int unsigned var;
  rand config_object cfg[2];

  constraint c_t_var1 {
    solve cfg[0].enable before solve cfg[0].var1;
    solve cfg[0].var1 before solve var1
    solve cfg[1].var1 before solve var1
    if ( cfg[0].enable)
      var1 == cfg[0].var1;
    else
      var1 == cfg[1].var1;
  }
  //similar constraint for var2
  
endclass

In the post_randomize function of the config_object, when I print the variables:

config_object[0].enable = 0;
config_object[0].var1 = 10
config_object[0].var2 = 15
config_object[1].enable = 1;
config_object[1].var1 = 12
config_object[1].var2 = 16
test_config.var1 = 12;
test_config.var2 = 16;

Thanks Dave!