Soft constraints must be followed by an expression

SystemVerilog
, ,
1

Hi All,

Section 18.5.13 Soft constraints of the LRM mentions

class Packet;
rand bit mode;
rand int length;
constraint deflt {
soft length inside {32,1024};
soft mode -> length == 1024;
// Note: soft mode -> {length == 1024;} is not legal syntax,
// as soft needs to be followed by an expression
}
endclass

Assume there are additional 2 random properties: rand int depth; rand int width

If user wanted to club multiple constraints ( within{ } ) as part of implication constraint, they would typically write it as ::

constraint deflt {
soft length inside {32,1024};
soft mode -> { length == 1024; depth == 1000 ; width == 2000; }
}

However as per LRM this would be illegal.

In such cases how should a user club multiple constraints ?

2

You can easily combine multiple boolean constraint expressions using the logical && (and) operator

soft mode -> length == 1024 && depth == 1000 && width == 2000;
``