Soft constraints must be followed by an expression

SystemVerilog
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1

Hi All,

Section 18.5.13 Soft constraints of the LRM mentions

class Packet;
rand bit mode;
rand int length;
constraint deflt {
soft length inside {32,1024};
soft mode -> length == 1024;
// Note: soft mode -> {length == 1024;} is not legal syntax,
// as soft needs to be followed by an expression
}
endclass

Assume there are additional 2 random properties: rand int depth; rand int width

If user wanted to club multiple constraints ( within{ } ) as part of implication constraint, they would typically write it as ::

constraint deflt {
soft length inside {32,1024};
soft mode -> { length == 1024; depth == 1000 ; width == 2000; }
}

However as per LRM this would be illegal.

In such cases how should a user club multiple constraints ?

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2

You can easily combine multiple boolean constraint expressions using the logical && (and) operator

soft mode -> length == 1024 && depth == 1000 && width == 2000;
``
3

Thanks Dave.

When tested on the main three EDA tools ( 2025 version ), I observe that they treat the following as legal syntax ( although LRM explicitly mentions it as illegal )

constraint deflt {
                       soft length inside {32,1024};
                       soft mode -> { length == 1024; } // Legal on EDA tools                       
                 }
4

Out of the 3 tools, one gives a warning. But they only work with simple forms that are easy to translate into the syntax I showed you. I think it’s because we all know how lazy SystemVerilog verification engineers are when it comes to writing code. I’d recommend sticking with the legal syntax form.

5

Hi Dave, why is the restriction only for soft constraints using implication operator ?

If I remove the soft keyword then I no longer observe the warning message from the 1 tool

constraint deflt {
                  length inside {32,1024};
                  mode -> { length == 1024; } // Why is this considered legal ?
                 }
6

The restriction isn’t limited to the implication operator. The following is also illegal:

soft mode -> unique {length, width};

What might be confusing is that the -> operator is used to represent both the logical implication operator in a Boolean expression and a constraint expression. Constraint expressions are supersets of Boolean expressions.

7

Unfortunately, Dave I am still not clear :frowning:

(1) What makes this illegal ?

I am not clear on the above. Could you please elaborate ?

(2) Section 11.4.7 Logical Operators of the LRM mentions logical implication ( → ).

The logical implication expression1 –> expression2 is logically equivalent to (!expression1 || expression2)

As per LRM

A constraint may be any expression containing operands of integral or real types only.

An expression can contain logical operators ( which includes → )

8

Let me answer in reverse order.

(2) Sometimes, the -> symbol is not a logical implication operator. Just like the symbol <=, depending on the context, it could mean a non-blocking assignment or a less-than-or-equal. In a constraint, the syntax after the -> operator must be a Boolean expression for it to be considered a logical implication. Otherwise, it is considered a constraint implication.

(1) The soft keyword must be followed by a boolean expression, which is essentially an integral expression that can be compared to zero. On the other hand, unique {length, width} is not an expression; it is a constraint. Consequently, the expression mode -> unique {length, width} cannot be considered a logical expression.

The SystemVerilog BNF syntax rules define this.

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