Size of Union in SystemVerilog

But for the Packed unions must contain types that are all the same size (# of bits).so in above example
typedef union {
bit [23:0] a;
bit [39:0] b;
} UN_A;
both the size of a and b must be same if that is not same i am facing an FATAL error saying The members of packed union must be the same size.
How to get the size as 40 for this example ??