Singleton example by dave

SystemVerilog
1 
const Root my_root = new(); // illegal
 Root my_root = Root::get();
 MyComponent me = new(“me”, my_root ); //race
 MyComponent me = new(“me”, Root::get() )

Is there static initialization order fiasco?
Dave said that it will appear.
But I don’t understand why line 3 has it.
In line 2 my_root should not be null because Root::get() must not return null.

2

If all these lines are static variable declarations, there is no defined order that these initializations take place as they are not executed as procedural code. That means it’s possible my_root has not executed its initialization before the initialization of me.

3

Why these lines will be static variable declaration when there is no static keyword before the variable?

4

They are static if declared at the top-level of module/interface/package. There is no other choice. If declared inside a procedural block, then there is a choice between static or automatic. If declared in a class, there is a choice between static or non-static (dynamically allocated when constructing the class).

5

So if I do this

 Root my_root = Root::get();
 MyComponent me;
me = new(“me”, my_root );

It can be guaranteed that the my_root in new() won’t be null?

6

You need to provide more context. If you mean

module top;
  Root my_root = Root::get();
  MyComponent me;
  initial me = new(“me”, my_root );
endmodule

The static initialization call to Root::get() is guaranteed to happen before the initial process starts.

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