In reply to Farhad:
In my personal opinion having a SV uvm testbench simplifies the point to point test scenario which would take longer and much more effort with formale due to the lots of assumes to be used. Give you a practical example: formal register verification is amazing which helps you to quickly verify power on reset value of many registers in 1 run. Nevertheless if you wanna just test 1 reg (a special one for instance whit some logic around it ) formal is still capable but not faster and effortless as the simple uvm test.
Hence a sv or uvm environment would still be required to test out directly some scenarios (just gave you one example) without the heavy duty of exploring all the possibilities like formal does. Anyway formal has been steadily becoming more adopted in my opinion and easy to setup.
Regards