Simulating Power-Up

SystemVerilog
3

In reply to Tudor Timi:

Hi Tudor. Yes, multiple simulation sessions are the way I will do it if there are no other convenient options. My initial resistance to multiple simulations stems from two issues: 1) it elevates the test flow from the SV code up to the Python code that is executing the test, and 2) the DUV contains non-volatile memory whose contents need to be preserved between power-ups. I would need to communicate this, and other information, to the next simulation run through files.

So yeah, not impossible, but it would be nice if there was something like:

duv duv_i (.*);

initial
begin
    force duv_i = 'X;
end