Signal starts in the middle of the clock

SystemVerilog
7

In reply to dave_59:

here is my original code:
virtual task run_phase(uvm_phase phase);

    `msg_uvm(UVM_LOW, "Reset done ...")

    //For some reason this synchronisation below is required here otherwise VCS will not
    //drive signals at all ... :-0

// @(pins.driver_cb);
if (active_mode) begin
@(posedge trgt_if.clk);
forever
begin
seq_item_port.get_next_item(req);
drive_pkt_txn(req);
seq_item_port.item_done();
end
end
endtask

in this case as I said the there are b2b transaction when the first on starts at the opposite clock edge

I’ve change it to the next:
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);

    `msg_uvm(UVM_LOW, "Connect phase complete ...") // Driver has to be derived from ovm_driver not intc_component
endfunction
// Get sequence items from sequencer
virtual task run_phase(uvm_phase phase);

    `msg_uvm(UVM_LOW, "Reset done ...")

    //For some reason this synchronisation below is required here otherwise VCS will not
    //drive signals at all ... :-0

// @(pins.driver_cb);
if (active_mode) begin
forever @(posedge trgt_if.clk)
begin
seq_item_port.get_next_item(req);
drive_pkt_txn(req);
seq_item_port.item_done();
end
end
endtask
extern task drive_pkt_txn(itp_trgt_seq_item txn);
endclass: itp_trgt_driver

and now the first transaction still starts at the opposite edge but there is one cycle of idleness between each two transactions…