Shifting on signed arithmetic

SystemVerilog
, , ,
4

In reply to Mitu Raj:

The Sign extension is not take care by the simple << operator you are getting the extension because the result is signed as well, and this extension happens after the shift.

As far as I remember the arithmetic shift will take care of in case of signed operands.


module tb;
  logic signed [3 : 0] a = 4'b1101; 
  logic signed [5 : 0] b, c;
 
  // these 2 are identical 
  assign b = (a << 1); 
  // This is not working properly since is always considering the value as negative 
  assign c = signed'(a << 1);
  
  initial begin
      #1;
      $display("a: %d or %b",a,a);
      $display("b: %d or %b",b,b);
      $display("c: %d or %b",c,c);
    end
endmodule

Result:
// Case A = -3
a: -3 or 1101
b: -6 or 111010
c: -6 or 111010
// Case A = 5
a: 5 or 0101
b: 10 or 001010
c: -6 or 111010

  1. The first statement does sign-extending to 6 bits first, and then shifting-
    eg: 0101 (+5) → 000101 → 001010 (+10)
    eg: 1010 (-6) → 111010 → 110100 (-12)

I do not think so how do you know the final sign if you do not perform the operation first. I believe the extension happens after. Regards