In reply to dave_59:
but then how the following works:
always_ff @(posedge sys_clk) begin
if (sys_rst)begin
a <= 1'b0;
b <= 1'b1;
end else begin
a<=b;
b<=a;
end
end
here, a and b will switch every clock cycle… so it does not seems like one overwrite the other or I don`t understand the meaning of “it gets overwritten by the next assignment”