You need to build a uvm testbench for your uvm_config_db set to work / make sense.
You did mention that you are new to System Verilog / UVM. You will need to do a lot more reading on UVM basics before you can get the piece of code you have to work.
If you are not interested in going the UVM route, and rather just stick to System-Verilog, you should just drop the uvm_config_db set and continue using just SV.