Hello , I am trying to override following sequences from build_phase of test .
virtual function void build_phase(uvm_phase phase);
env_configuration::type_id::set_type_override(config_one::get_type()); //config_one is a class having configurations
sequence_base::type_id::set_type_override(default_sequence_1::get_type());
env_configuration::type_id::set_type_override(config_two::get_type()); // different configurations .
sequence_base::type_id::set_type_override(default_sequence_2::get_type());
// Execute the build_phase of AFTER all factory overrides have been created.
super.build_phase(phase);
endfunction
I understand why above code is not working (only the last ovverides executes ). However I would like to know how do I override it in this way sequentially , one after the another . So first set of ovverides executes then another. The requirement is I can changes configurations from overrides .
In reply to sarth21:
You can do an override for the default_sequence only once. In your case I’d recommend to create a new sequence which has both your sequences inside (called in a series). Then you can override the new sequence.
In reply to sarth21:
Doing something like this might involve restructuring your sequences. You might try a hierarchy of sequences where one sequence calls a series of other sequences.
Another option is creating an array of sequences. You could use a queue and push/pop sequences on/off the queue.
If you come back and tell us you can’t modify the architecture of your test bench, then you’re going to have to give us a lot more information about how it’s currently structured.
In reply to dave_59: .
Thanks for the reply . I understood this approach wont work . So I will be doing the virtual sequences approach without overrides . Thanks . Have a great day :)
In reply to chr_sue:
Thanks for the reply . I understood this approach wont work . So I will be doing the virtual sequences approach without overrides . Thanks . Have a great day :)