Seminar Notification: Silicon Valley Design and Verification IP Forum - San Jose, CA

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Silicon Valley Design and Verification IP Forum

Overview:

The microelectronics industry is witnessing a growing reliance on the integration of design IP that implements an ever increasing variety of industry standard interfaces required for today's complex designs. This places an additional verification burden of ensuring both functional correctness and interoperability. This forum brings together DIP and VIP integrators and partners, offering the opportunity to network with your peers, hear from technical experts, and explore the latest IP-driven verification trends and solutions.

Keynotes:

  • Conquering the New IP Economy - presented by Harry Foster, Mentor, a Siemens Business
  • Trends and Requirements in High Speed Interface Verification - presented by Niraj Mathur, Rambus

Sessions:

  • MIPI® CSI-2 TX Verification
  • USB 3.1 Verification Challenges
  • The Need for Speed: PCIe® Gen 4 Verification
  • Leveraging the Latest DDR & Flash Memory Models
  • Where No Man Has Gone Before: Enterprise Ethernet PHY Verification
  • Creating a Thorough Verification Environment in Less Than Two Days

Session Presenters:

Featured Presenters at the Silicon Valley Design and Verification IP Forum

Session recordings now available.