Hi,
if we have structure format as output how we will verify the output structure in scoreboard in uvm.
For Example;
module dut_name( input [63:0]data, input ctrl_req1,ctrl_req2, input [15:0]addr1, input [15:0]addr2, output tb_structure ms_struct1, output tb_structure ms_struct2);
/// ----logic-----
endmodule
above code will be dut.
logic Description:
Inside the DUT, there are three main components: DataCombiner, Scheduler, and RAM. The DataCombiner combines data into a structured format, which is then stored in RAM. The Scheduler accepts control signals (ctrl_req1, ctrl_req2) and address inputs (addr1, addr2) and uses them to send the stored structures to either ms_struct1 or ms_struct2
can anyone suggest methods to verify the structures in scoreboard.