In reply to ben@SystemVerilog.us:
Hi,
always @(enable_tb) begin
scale1 =1;
#15 scale2 = 1;
end
In this code I want every 15 cycles after scale1 and scale2 variables should be toggled untill the variable enable_tb =1.
like if first 15 cycles scale1 =1,then after 15 cycles scale1 should go to zero and scale2 should be 1 for 15 cycles.
again after 15 cycles scale2=0 and scale1=1.
this process continues untill enable_tb =1;
if enable_tb =0; then this both scale should be zero