In reply to wiki458:
when we are working out of clock we should have some path for the program that we write considering verilog we have stratified event queue so that every condition or evaluation of variables and the results are taken into particular regions so that the execution is perfect.
In the same way we have regions for system verilog assertions also and each regions have its own work like UVM phases,and that too we have two types of assertions one is immediate assertions that are used for combinational circuit evaluations and these are executed based on event regions and the other is concurrent assertions which are based on clock.
I explained upto my knowledge let em know if I am wrong