Sampling point of Assertions

SystemVerilog
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In reply to sapsharma19:

All the systemverilog/verilog events happens in same clock cycles and they are repeated for each clock. Read following paper for better understanding of systemverilog events:

http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

I think it’s better to refresh SV concepts before jumping on to assertions.

Thanks,
Rohit