Sampling point of Assertions

In reply to GMZlate:
I believe that what you are saying is true. However the following example should clarify things. Simulation must reflect how harware behaves. Consider the following example where the D output of a D FF is fed back to its input through an AND gate.


always_comb begin
            din = dout && enb; 
        end 
        
        always  @(posedge clk)  begin 
            dout <= !din;
        end 
 

Assumng 0 setup and hold time, andy change to dout or enb re-evaluate din.

@(posedge clk) dout will change its value in the NBA region. The loop through the Active region re-evaluates din (since ther was a change). However, the dout <= !din; will NOT be re-evaluated again, even with zero setup and hold times.
I believe that this is what you were saying. Below is my test code.

 
import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;    
    bit clk, din, dout, enb;
   	default clocking @(posedge clk); endclocking
        initial forever #10 clk=!clk;   
        always_comb begin
            din = dout && enb; 
            //$display(" at %t in comb: a = %0d", $time, a); 
        end 
        
        always  @(posedge clk)  begin 
            //$display(" at %t in always: a = %0d", $time, a); 
            dout <= !din;
        end 
        
        initial begin 
            bit va; 
            repeat(20) begin 
                @(negedge clk);   
                if (!randomize(va)  with 
                {va dist {1'b1:=6, 1'b0:=1};      
            }) `uvm_error("MYERR", "This is a randomize error")
            enb <= va;
        end 
        $stop; 
    end 
endmodule   

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  1. VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
  2. http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
  3. “Using SVA for scoreboarding and TB designs”
    http://systemverilog.us/papers/sva4scoreboarding.pdf
  4. “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
    October 2013 | Volume 9, Issue 3 | Verification Academy
  5. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy