In reply to ben@SystemVerilog.us:
Yes, an 0 in the always block is expected. If you want to show that changing w changes the NBA assignment you need to make sure that a <= w happens between the w = 1 and w = 0. However, in your example, the a <= w is scheduled before the always_comb (according to your output) and the value used in evaluating the RHS IS 0. So for sure your always example should output 0.