In reply to ben@SystemVerilog.us:
In reply to pawan:
Sorry, but you are incorrect here. The signals are steady just before the clocking event.
After the clocking event, you have all these regions (like active, NBA)when the signal change values. There are many cases when, because the evaluation of logic is sequential in a computer, you would have zero time glitches in the Active region; in fact, this is why you have deferred assertions. Thus, your statement that the signal is steady just at the edge of clock not before is incorrect. How could it be unsteady “before”, but “steady” after?
After the clock, the signals change, and are steady in the Posponed Region. So, in which Region do you want to do your tests? Active, Inactive, Observed, NBAor Posponed?
If you can identify which Region you want to use, how would you write this? you can’t.
In the initial states, you may have Xs, and after the clock edge, it is steady. Your tests should start on a steady reset design.
Again, this is exactly what you want, the sampling in the Prepone region, just before the clock edge, and not a delta time after the clock edge. If you are worried about the Xs, your test should start on a steady reset system. You have assertion controls to turn you assertions ON/OF. Turn them ON on a steady system.
RTL simulation is designed to emulate real designs with delays and setup and hold requirements, even though you can run it with gates and FF with 0 delays. This is why you have the evaluation regions, don’t make up your own regions, you’re setting up for failure.
Think real designs. Review and understand the regions.
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There is nothing right or wrong here I am telling u how my design is behaving and wanted to know if there is a sophisticated solution for the same