In reply to p*9s$eW:
- testbench.sv should be called cpu_test.sv as that is the core functionality in the file
- A package is never included, only imported inside a module.
- Don’t define anything outside a module / interface / package. Th.at is not really a global name space
- Compile the packages first, then then the interface, and finally the modules.
- The files with single classes should end with .svh for “SystemVerilog header”. This shows that these files are only included in a package, never compiled directly. Only .sv files are compiled directly.
- A better name for the typedefs package would be cpu_rtl_pkg.sv