In reply to p*9s$eW:
You can have a scoreboard that raises an objection waiting for something to happen to lower that objection.
If your program is self checking, you can have halt at one particular PC address for a pass, another PC address for a fail. You can have a monitor on the address bus and send a transactions to the scoreboard. The scoreboard can then decide if the test passes or fails when one of the addresses are accessed. It should also have a timeout based on how long the program is supposed to run.
The OpenHW Group is doing something very similar by creating a virtual peripheral which is just a set of registers used by the test. The UVM RAL can be used to monitor the memory bus and a callback is can be set up to trigger the end of test when a particular register is written to.
BTW, that OpenHW page uses the term run_phase, when it really means main_phase.