In reply to chr_sue:
In reply to verif_learner:
Did you see the following line in your simulation log-file:
reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase
This is an indication the run_phase has been completed.
Again could you please show your run_phase implementation.
No. I don’t see that.
This is what I see towards the end.
INT TST SEQ
$finish called from file “…/tb/dma_tb.sv”, line 312.
Looks like testbench is executing $finish and not allowing UVM to finish gracefully.
For my understanding, when $finish is executed, I assume simulation would end immediately irrespective of any other threads active