Round Robin Assertion

SystemVerilog
2

In reply to Ammu786:
// Hi bit has higher priority. Every 4 clocks, req bits gets shifted.
// May need a better approach on this point, Spec is vague on this


module top;
  timeunit 1ns;  timeprecision 100ps;    
  `include "uvm_macros.svh"   import uvm_pkg::*;
  bit[15:0]  reqbit; // debug 
  bit clk, reset_n;
  bit[15:0] req, rb_req, grnt; 
  initial forever #10 clk = !clk;
  event e1, e2, e3;  // debug
  // Round Robin every four clk 
  // rb_req becomes the requests for arbitration  
  initial forever begin // USE A DIFFERENT ALGORTIHM 
    repeat(4) @(posedge clk); 
    rb_req <= {req[0], req[15:1]};  // ??     
  end

  always @(posedge clk) begin 
    for (int i=15; i> 0; i--) begin
    	if (rb_req[i])
    		begin 
              -> e1; reqbit=i; 
    		  ap_rb:  assert property (@(posedge clk) ##1 grnt[i]==1'b1 && $onehot(grnt));  
              ap_rbg: assert property (@(posedge clk) ##1 grnt[i]==1'b1);  // for debug 
    		  break; 
    		end 
           
    end
  end

  ap_zero_req: assert property(@(posedge clk) req==0 |=> grnt==0); 
endmodule