In reply to vvv:
You have not compiled or run your model did you?
With your for (genvar i = 0; i<4; i++)
for (genvar j=i+1; j!=i; j++)
I got error message like
** Error: roundrb.sv(23): (vopt-2134) Evaluation of a generate loop has exceeded the iteration limit of 100000.
# ** Note: roundrb.sv(23): (vopt-2129) Design elaboration has evaluated 100001 loop generated blocks....
To verify your model, get one that compiles and eleborates OK.
Use constrained-random tests to test a small dample, and check it out. Below is an example for a simple driver:
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(req, gnt, prev_grnt) with
{ req inside {0, 1, 2, 4}; // dist {1'b1:=1, 1'b0:=3};
gnt inside {0, 1, 2, 4}; // dist {1'b1:=1, 1'b0:=2};
prev_grnt inside {0, 1, 2, 4};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
BTW, add labels to you assertions. The @ posedge(clk) (<<-- incorrect) should be written as @(posedge clk)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115