In reply to Jad:
For 2 signals, it is easy. However, if you have a large vector, you’ll need to add some supporting logic to keep track as to who next can get the grant if the req is asserted.
module roundrobbin;
bit clk;
bit[1:0] req, grnt;
bit[3:0] r, g, grants;
ap_grnt1_after2: assert property(@(posedge clk)
req[1] && !grnt[1] && $fell(grnt[0]) |=> grnt[1]);
ap_grnt1_no2: assert property(@(posedge clk)
req[1] && $countones(grnt)==0 |=> grnt[1]);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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