Reversing the array elements in a array without using reverse keyword

SystemVerilog
,
4

In reply to Manikanta Kopparapu:

With below print it does not mean, only first and last index generating conflict.
This is just showing list of constrains/condition involved for constraints conflict.


rand bit[7:0] array_1[0]; // rand_mode = ON 
rand bit[7:0] array_1[4]; // rand_mode = ON 
 
constraint addr_unique_values    // (from this) (constraint_mode = ON) (arrays_example.sv:118)
{
   (array_1[0] == 0);
   (array_1[4] == 4);
}
constraint WITH_CONSTRAINT    // (from this) (constraint_mode = ON) (arrays_example.sv:142)
{
   (array_1[4] == array_1[0]);

See, below result in this i have just changed array from 5 to 10. It shows only array[0] and [9].



rand bit[7:0] array_1[0]; // rand_mode = ON 
rand bit[7:0] array_1[9]; // rand_mode = ON 

constraint addr_unique_values    // (from this) (constraint_mode = ON) (testbench.sv:4)
{
   (array_1[0] == 0);
   (array_1[9] == 9);
}
constraint WITH_CONSTRAINT    // (from this) (constraint_mode = ON) (testbench.sv:27)
{
   (array_1[9] == array_1[0]);
}

So, as per above example it does not mean only array[0] and array[9] has conflict only.
As, per my understanding during randomization any condition is not satisfying/contradicting randomization fail will come.

In your case original constraints was like below.


 constraint addr_unique_values{ 
    foreach(array_1[i]) array_1[i] == i;
  }
 
  //Equivalent
   constraint addr_unique_values{ 
    array_1[0] == 0;
    array_1[1] == 1;
    array_1[2] == 2;
    array_1[3] == 3;
    array_1[4] == 4;
  }

However, during second randomization by using in-line constraints you are trying to apply different value ( EX:- array[0] = array[4] ).
which is contradicting to original hard constraint.

I hope now its clear to you.

Thanks!