Reversing a string

SystemVerilog
9

In reply to sarang:

Hi Sarang,

Each character in a string is stored as 8 bits. So for reversing we need to use 8. If you use 4, then half of the bits gets reversed which does not give correct result. Lets take an example of a string with two characters and you can find the solution

module tb;
  string s1 = "is";
  string s2;
  initial
    begin
      $display("string s1 in binary format = %b ", s1);
      s2 = {<<8{s1}};
      $display("reversed string=%b and string is %s", s2,s2);
      s2 = {<<4{s1}};
      $display("reversed string=%b and string is %s", s2,s2);
    end
endmodule

Output will be
string s1 in binary format = 01101001 01110011
reversed string=01110011 01101001 and string is si
reversed string=0011 0111 1001 0110 and string is 7?

ASCII VALUE OF i is 01101001
ASCII VALUE OF s is 01110011
ASCII VALUE OF 7 is 00110111
ASCII VALUE OF ? is 10010110