A assertion for reset where the reset is active low , the reset should dessert asynchronously , and after two clock cycle it should assert synchronously .
I tried in this way
property reset_sync(bit clk ,rst);
(@(negedge rst) 1’b1 |-> (@(posedge clk) ##1 $stable(rst)[*2] ##1 @(posedge clk) !($stable(rst))));
endproperty
@ben2 @dave_59 can you help me with this ,for the above assertion it is failing in some cases, can you correct it as per the requirement