Replication in assignment pattern not working on queue of structure

SystemVerilog
,
2

In reply to rishikpillai90:

‘var’ is a keyword in SystemVerilog used for a variable declaration. If the type is not specified, then var defaults to logic type. Just rename your variable queue and it should solve the problem.

The following should work fine.

module top();
  typedef enum {H_ENUM,A_ENUM} A;
  typedef enum {I_ENUM,B_ENUM} B;
  typedef enum {J_ENUM,C_ENUM} C;
  typedef enum {K_ENUM,D_ENUM} D;
  
  typedef struct {
 A a;
 B b;
 C c;
 D d;
} lp_s;    //A,B,C,D : integer enums
 
lp_s vari[$] = '{    //No difference in result even with unpacked array concatenation
 '{a:A_ENUM, b: B_ENUM, default:0}
};
  initial begin
    #1;
    $display(vari);
  end
endmodule

For more information, var is explained in IEEE 1800-2012 Section 6.8.