repeat vs for loop control variable

SystemVerilog
1

How repeat and for loops handle loop variables internally in SystemVerilog?

Example:

int n = 5;

repeat(n) begin
  n++;
end

for (int n = 0; n < 6; n++) begin
  n++;
end

repeat(n) seems to evaluate n only once, while for reevaluates the condition every iteration.

How does the simulator handle these internally?

2

The IEEE 1800-2023 SystemVerilog LRM explicitly defines this behavior. The LRM mandates that the repeat(expression) construct evaluates the expression only once and then use a hidden counter to control the number of loop iterations.