Repeat loop

SystemVerilog
,
1

We can see in this example that we have set the field to 6 in repeat loop. As a result of this, the repeat loop will run a total of six times before terminating.

module code();
  reg[2:0] x,y;
initial 
begin 
  x = 0;
  y = 10;
  repeat(6) 
  begin
   	 x = x + 1;
     $display("x = %d",x); 
  end 
end 
endmodule

now instead of that I am changing the repeat loop below like this

y = 10;
repeat(y) 
  begin
   	 x = x + 1;
     $display("x = %d",x); 
  end

How many times does the following repeat loop will execute?
it will not execute. please explain me what happened in this scenario.

2

In reply to anvesh dangeti:

It would help if you posted a complete example that demonstrated your issue.

Also, since the variable y is only 3 bits, the maximum value you can store is 7. You can’t store the value 10 properly.


module code();
  int x,y;

  initial begin 
    x = 0;
    y = 10;
    repeat(y) begin
      x = x + 1;
      $display("x = %d",x); 
    end 
  end 
endmodule
3

In below code when I am changing the “a” value inside the loop it don’t effect the repeat loop iterations? The repeat loop will execute old value of “a” or new updated value of “a”

module code();
  int a,b;
initial 
begin 
  a = 6;
  b = 20;
  repeat(a) 
  begin
   	 a = b+1;
    $display("a = %d",a); 
  end 
end
endmodule
4

In reply to anvesh dangeti:

The repeat loop iterates a fixed number of times; you cannot change the iteration count once into the loop.