Repeat loop

SystemVerilog
,
3

In below code when I am changing the “a” value inside the loop it don’t effect the repeat loop iterations? The repeat loop will execute old value of “a” or new updated value of “a”

module code();
  int a,b;
initial 
begin 
  a = 6;
  b = 20;
  repeat(a) 
  begin
   	 a = b+1;
    $display("a = %d",a); 
  end 
end
endmodule