Related to SV constraint

SystemVerilog
1

when we don’t use any random variables at this time. if we want to write a constraint. for some pattern like 0 → 1 → 2 → 0.
if 0 comes in the 1st randomization then in next randomization 1 will come and next 2 and next 0 like this the pattern is.

i write this constraint.

	std::randomize(a) with {(a==0) -> (a==1) -> (a==2) -> (a==0) ;};

please check the above one whether it is correct or not and explain the above constraint and share your knowledge

Thanks in Advance

2

In your example a is is random variable. Its value is undefined during randomization. You would have to use a cast const'(a) to refer to its value prior to randomization.

Also you cannot write implication constraints in series like that. It’s the same as writing A < B < C which is the same as (A < B) < C. You could write this as A<B && B<C or A<B;B<C

std::randomize(a) with {
    const'(a)==0 -> a==1;
    const'(a)==1 -> a==2;
    const'(a) >1 -> a==0;
}
3

Hi Dave,

How does using the cast to const helps here?
Never saw this being used in constraint context.

Thanks

4