In reply to Phill_Ferg:
Not sure what simulator you are using if you don’t know freeze vs deposit. In Modelsim, you have the choice - a force deposit will merely place the value on the net and that net is then free to change if something else wants to drive that net. A freeze force freezes that net so nothing else can change it until the force is removed. From everything I’ve read (and my experience) a SystenVerilog force acts as a freeze - you need to do a release if you want to allow the HW to control it. Modelsim also has a drive force, but I’ve never used that. As far as the mechanism used by UVM, would that be simulator-dependent? Seems to be that it would necessarily need to be implemented via a SV force/release so as not to impede the HW, unless it directly interacts with the simulator and it thus a tool-dependent implementation.
Sounds to me like back door writes, while possible, could be problematic and should be avoided. I would just a soon do frontdoors, as then you are not bypassing any other HW side-effects. For example, we have registers where, if you write one, others will automatically be written to that same value as well. It obviously depends upon HW implemenation. Seems to be that backdoor accesses are be used at your own peril.