In reply to krgarvens:
If you have any experience with Modelsim/Questasim you will recognise the “force” feature that allows you to change the value of any signal in the middle of a simulation.
There is nothing to stop the simulator stopping in between delta cycles and changing a value. All the back door access does is provide an api to do something very similar but from a systemVerilog perspective. Reading a value in the middle of the simulation if the hierarchical path of the simulation is known has been around for ages.
To get your path, compile and run your design, then look through the hierarchy browser in the simulation. You really should be able to trace your hierarchy through the VHDL/Verilog DUT without a problem
I believe this section talks a lot about back door access.