In reply to chr_sue:
I thought since this was of type uvm_reg_sequence already has a default parameters
class uvm_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item)) extends BASE;
`uvm_object_param_utils(uvm_reg_sequence #(BASE))
ok so here is my question, what kind of sequencer do i run a uvm_reg_sequence on?
At the moment i am running it on the sequencer that connects to the adaptor.
Also, when i look at the call stack it appears that my sequence is fine - the register block is processing the request and communicating to the adaptor. The problem appears to be the adaptor translation between the *_item coming from the register block and the *_item going to the driver.
Call Stack window
| # | In | Line | File | Address |
|---|---|---|---|---|
| 0 | Function uvm_pkg/uvm_root::die | 135 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_root.svh | return 0x59138991 |
| 1 | Function uvm_pkg/uvm_default_report_server::execute_report_message | 732 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_server.svh | return 0x590a8131 |
| 2 | Function uvm_pkg/uvm_default_report_server::process_report_message | 628 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_server.svh | return 0x590a624c |
| 3 | Function uvm_pkg/uvm_report_handler::process_report_message | 333 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_handler.svh | return 0x590b58f8 |
| 4 | Function uvm_pkg/uvm_report_object::uvm_process_report_message | 251 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_object.svh | return 0x590c3d5a |
| 5 | Function uvm_pkg/uvm_report_object::uvm_report | 146 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_object.svh | return 0x590c1cb2 |
| 6 | Function uvm_pkg/uvm_report_object::uvm_report_fatal | 239 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/base/uvm_report_object.svh | return 0x590c372d |
| 7 | Function uvm_pkg/uvm_sequencer_param_base::send_request | 277 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/seq/uvm_sequencer_param_base.svh | return 0x593ed8b2 |
| 8 | Task uvm_pkg/uvm_sequence_base::finish_item | 1027 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/seq/uvm_sequence_base.svh | return 0x591a0778 |
| 9 | NamedBeginStat uvm_pkg/uvm_reg_map::do_bus_write/foreach_value | 1941 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/reg/uvm_reg_map.svh | return 0x592b08e6 |
| 10 | Task uvm_pkg/uvm_reg_map::do_write | 1784 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/reg/uvm_reg_map.svh | return 0x592b590a |
| 11 | NamedBeginStat uvm_pkg/uvm_reg::do_write/built_in_frontdoor | 2278 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/reg/uvm_reg.svh | return 0x59216731 |
| 12 | Task uvm_pkg/uvm_reg::write | 2146 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/reg/uvm_reg.svh | return 0x59209e74 |
| 13 | Task block_C_tests_pkg/RAL_test_seq_c::body | 138 | ../tb/tests/RAL_seq_lib.svh | return 0x597ceea1 |
| 14 | Task uvm_pkg/uvm_sequence_base::start | 347 | /home/APPS/questasim/10.6b/questasim/linux/../verilog_src/uvm-1.2/src/seq/uvm_sequence_base.svh | return 0x59198f07 |