In reply to chr_sue:
Christoph! We’ve met on a UVM training course in Ringwood! I hope you are well.
My apologies, i missed your first question and put down my own thoughts.
ok from my test
RAL_test_seq_c chain_config;
...
chain_config = RAL_test_seq_c::type_id::create("chain_config");
// set the register block block in for the sequence
chain_config.starting_phase= phase;
chain_config.set_reg_model(tb.regmodel);
// Set the same sequencer that the reg model uses
elicia_config.start(tb.APB_mseqr);
Within the RAL_test_seq_c including the base class
virtual class RAL_base_seq_vc extends uvm_reg_sequence #();
registers_pkg::register_block model ;
function new(string name="RAL_base_seq_vc");
super.new(name);
endfunction
// Raise objection in pre_body
virtual task pre_body();
if (starting_phase!=null) begin
`uvm_info("RAL_BASE_SEQ",$sformatf("%s pre_body() raising %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM);
starting_phase.raise_objection(this);
end
endtask
// Drop objection in post_body
virtual task post_body();
if (starting_phase!=null) begin
`uvm_info("RAL_BASE_SEQ", $sformatf("%s post_body() dropping %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM);
starting_phase.drop_objection(this);
end
endtask
function match(string s1,s2);
int l1,l2 ;
l1 = s1.len() ;
l2 = s2.len() ;
match = 0 ;
if( l2 > l1 ) return 0;
for(int i = 0;i < l1 - l2 + 1; i ++)
if( s1.substr(i,i+l2 -1) == s2) return 1;
endfunction
//function for getting the value of model field
//@return model field value
virtual function registers_pkg::register_block model get_reg_model();
return model;
endfunction
//function for setting a new value for modele field
//@param model - new value of the model field
virtual function void set_reg_model(registers_pkg::register_block model);
this.model = model;
endfunction
endclass:RAL_base_seq_vc
class RAL_test_seq_c extends RAL_base_seq_vc;
`uvm_object_utils(RAL_test_seq_c)
function new(string name="RAL_test_seq_c");
super.new(name);
endfunction
virtual task body();
uvm_status_e status;
uvm_reg_data_t data;
assert (model != null) else
`uvm_fatal("RAL_TEST_SEQ","Cannot get reg model");
model.CONFIG_STREAM_r.write(status, 'h05010501, .parent(this) , .path(UVM_FRONTDOOR) );
`uvm_info("RAL_TEST_SEQ", {$sformatf("Front door write: %0h with status %0s",'h05010501 ,status)} , UVM_LOW);
endtask : body
endclass: RAL_test_seq_c
I will also include my test bench linkage between my register model, the adaptor and the sequencer.
function void block_C_tb_c::build_phase(uvm_phase phase);
super.build_phase(phase);
...
reg2apb_adapter = amiq_apb_ex_reg_pkg::amiq_apb_ex_reg_reg2apb_adapter::type_id::create("reg2adb_adapter", this);
`uvm_info("block_C_TB", {$sformatf("Created: %0s",reg2apb_adapter.get_full_name())} , UVM_LOW)
apb2reg_predictor = amiq_apb_ex_reg_pkg::amiq_apb_ex_reg_apb2reg_predictor::type_id::create("apb2reg_predictor", this);
`uvm_info("block_C_TB", {$sformatf("Created: %0s",apb2reg_predictor.get_full_name())} , UVM_LOW)
regmodel = registers_pkg::register_block::type_id::create("regmodel",this);
regmodel.build();
regmodel.reset("HARD");
`uvm_info("block_C_TB", {$sformatf("Created: %0s",regmodel.get_full_name())} , UVM_LOW)
...
end function
function void block_C_tb_c::connect_phase(uvm_phase phase);
super.connect_phase(phase);
...
if($cast(APB_mseqr, apb_env.master_agent.sequencer) == 0) begin
`uvm_fatal("block_C_TB", "Could not cast to amiq_apb_master_sequencer")
end
`uvm_info("block_C_TB", {$sformatf("Set Sequencer in the top testbench : %0s",APB_mseqr.get_full_name())} , UVM_LOW)
// Connect up the register model
if(regmodel.get_parent()== null) begin
// Set the frontdoor sequencer and register adapter on the default_map member of the serial register model.
regmodel.default_map.set_sequencer(APB_mseqr, reg2apb_adapter);
apb_env.master_agent.monitor.output_port.connect(apb2reg_predictor.bus_in);
//Setup Register prediction
apb2reg_predictor.map = regmodel.default_map;
// Set the predictor adapter:
apb2reg_predictor.adapter = reg2apb_adapter;
// Set the base address in the system
regmodel.default_map.set_base_addr('h0);
// Set the auto predict off since a predictor needs to be used for coverage
regmodel.default_map.set_auto_predict(0);
end
...
end function
At the moment i am struggling to understand exactly what is not being set correctly. As you might have gathered i am using my register model with this APB code. I have executed normal sequences to read and write across the interface but the register layer link is a quite mysterious.