In reply to ben@SystemVerilog.us:
That is the most realistic explanation, but not how SystemVerilog is defined (See section 4.7 Nondeterminism in the IEEE 1800-2017 SystemVerilog LRM). By definition, only the relative order of statements with a single thread are guaranteed. Relative ordering between threads executing within the same active region cannot be relied upon.
Two places where the “single executing thread” model breaks down is when the simulation is spread across multiple cores, and optimizations that tie together what looks like independent threads into a single monolithic thread.