Regarding 'followed by' property #=#

SystemVerilog
,
2

In reply to MICRO_91:
The followed-by operators #-# and #=# concatenate a sequence and a property. The followed-by operators are of the following forms for the definition of a property:


property_expr ::=  
 ...
 | sequence_expr |-> property_expr  // same cycle 
 | sequence_expr #-# property_expr  // same cycle 

 | sequence_expr |=> property_expr  // next cycle  
 | sequence_expr #=# property_expr  // next cycle 

// Example from my SVA book: 
property p_BusAccess (bus_req, bus_ack);    
  (bus_req  |-> ##[1:7]  bus_ack); 
endproperty : p_BusAccess         
ap_DMA_BusAccess : assert property(@ (posedge clk) 
           $rose(dma_command) |=> (dma_req ##[1:3] dma_ack) // sequence 
                                      #=#  p_BusAccess(req, ack)); // property

Ben Cohen
Ben@systemverilog.us
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